Lam Research Kiyo series products guide
KIYO series products: reaction ion etching (RIE)
Interconnection, advanced memory, separation and power component, pattern, sensors and sensors, electrocarmiography, analog and hybrid signal
Conduct etching technology is used to engraving "active" electrical materials in semiconductor elements. Even if these micro -structures have slightly mutated, they will cause electrical defects and affect component efficiency. In fact, because these structures are very subtle, the progress of the etching process is breaking through the boundaries of physical and chemical laws.
Lam Research's Kiyo® series products can provide precision and stabilize the excellent effectiveness required for these conductor structures with high productivity. For some applications, through our RELANT® system, some models can also be selected as a renovation product, which can provide the same quality assurance and efficiency as the new system with lower ownership.
Industry Challenges
As the semiconductor industry continues to slightly shrink the key structure size and improves the effectiveness of the component, the conductor etching process is facing various challenges, including smaller structures, new materials on wafers and new crystal structures. Due to the reduction of the structure size, the etching process not only needs to be performed by each structure, but also the entire wafer -level precise control. In addition, the metal gates and High-K materials in the component stack also require the advanced multi-layer thin film etching capacity. Advanced chip designs will also appear at the same time such as Recessed Channel and 3D gate electrical crystals, as well as the etching structure of traditional flat -type electrocarmiography. In addition, the dual and Quadruple Patterning technology that can overcome the micro -shadow process of less than 20nm is required to define and remake the pattern on the wafer.
Key Customer Benefits
Through the symmetrical cavity design, the industry's leading electrostatic chuck technology, and the independent process variable function, it can achieve excellent uniformity and reapability
Through in-situ etching function, continuous plasma, and advanced Waferless Auto-Clean technology, it can achieve high productivity and low-defective multi-film stacking stacking.
Using exclusive Hydra® technology that can be modified input pattern variability can increase the uniformity of key size (CD)
Through the plasma -assisted atom layer etching (ALE) technology, atomic variant control can be achieved by the production verification production volume
Product Offerings
Versys® Kiyo®
Versys® Kiyo45 ™
KIYO® C series
Kiyo® E series
Kiyo® F series
Key Applications
Shallow groove isolation
Source/DRAIN
High-K/metal gate pole
FINFET and Tri-Gate
Dual and quadruple exposure
3D NAND
Interconnection, advanced memory, separation and power component, pattern, sensors and sensors, electrocarmiography, analog and hybrid signal
Conduct etching technology is used to engraving "active" electrical materials in semiconductor elements. Even if these micro -structures have slightly mutated, they will cause electrical defects and affect component efficiency. In fact, because these structures are very subtle, the progress of the etching process is breaking through the boundaries of physical and chemical laws.
Lam Research's Kiyo® series products can provide precision and stabilize the excellent effectiveness required for these conductor structures with high productivity. For some applications, through our RELANT® system, some models can also be selected as a renovation product, which can provide the same quality assurance and efficiency as the new system with lower ownership.
Industry Challenges
As the semiconductor industry continues to slightly shrink the key structure size and improves the effectiveness of the component, the conductor etching process is facing various challenges, including smaller structures, new materials on wafers and new crystal structures. Due to the reduction of the structure size, the etching process not only needs to be performed by each structure, but also the entire wafer -level precise control. In addition, the metal gates and High-K materials in the component stack also require the advanced multi-layer thin film etching capacity. Advanced chip designs will also appear at the same time such as Recessed Channel and 3D gate electrical crystals, as well as the etching structure of traditional flat -type electrocarmiography. In addition, the dual and Quadruple Patterning technology that can overcome the micro -shadow process of less than 20nm is required to define and remake the pattern on the wafer.
Key Customer Benefits
Through the symmetrical cavity design, the industry's leading electrostatic chuck technology, and the independent process variable function, it can achieve excellent uniformity and reapability
Through in-situ etching function, continuous plasma, and advanced Waferless Auto-Clean technology, it can achieve high productivity and low-defective multi-film stacking stacking.
Using exclusive Hydra® technology that can be modified input pattern variability can increase the uniformity of key size (CD)
Through the plasma -assisted atom layer etching (ALE) technology, atomic variant control can be achieved by the production verification production volume
Product Offerings
Versys® Kiyo®
Versys® Kiyo45 ™
KIYO® C series
Kiyo® E series
Kiyo® F series
Key Applications
Shallow groove isolation
Source/DRAIN
High-K/metal gate pole
FINFET and Tri-Gate
Dual and quadruple exposure
3D NAND